As integrated circuit geometry continues to plunge into the deep sub-micron regime, it becomes increasingly difficult to satisfy the requirements of high performance microprocessor applications for rapid circuitry speed. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the R×C product, the more limiting the circuit operating speed. Miniaturization requires long interconnects having small contacts and small cross-sections. Accordingly, continuing reduction of design rules into the deep sub-micron regime requires decreasing the R and C associated with interconnection paths. Thus, low resistivity interconnection paths are critical to fabricating dense, high performance devices.
One way to increase the control speed of semiconductor circuitry is to reduce the resistance of a conductive pattern. Copper (Cu) is considered a viable alternative to aluminum (Al) for metallization patterns, particularly for interconnect systems having smaller dimensions. Cu has a lower bulk resistivity and potentially higher electromigration tolerance than Al. Both the lower bulk resistivity and higher electromigration tolerance improve circuit performance. A conventional approach to forming a Cu interconnection involves the use of damascene processing in which openings are formed in an interlayer dielectric (ILD) and then filled with Cu. Such damascene techniques typically include single as well as dual damascene techniques, the latter comprising forming a via opening in communication with a trench opening and simultaneously filling by metal deposition to form a via in communication with a metal line.
However, Cu is a mid-gap impurity in silicon and silicon dioxide. Accordingly, Cu diffusion through interlayer dielectrics, such as silicon dioxide, degrades the performance of the integrated circuit. A conventional approach to the diffusion problem comprises depositing a barrier material to encapsulate the Cu line. Typically diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium tungsten (TiW), and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between the Cu and the ILD, but includes interfaces with other metals as well. In depositing Cu by electroless deposition or electroplating, a seedlayer is also typically deposited to catalyze electroless deposition or to carry electric current for electroplating. For electroplating, the seedlayer must be continuous. However, for electroless plating, very thin catalytic layers can be employed in the form of islands.
Conventional Cu interconnect methodology typically comprises planarizing after Cu deposition, as by chemical-mechanical polishing (CMP), such that the upper surfaces of the filled trenches are substantially coplanar with the upper surface of the ILD. Subsequently a capping layer, such as silicon nitride, is deposited to complete encapsulation of the Cu inlaid metallization. However, adhesion of such a capping layer as to the Cu inlaid metallization has been problematic, and Cu diffusion along the surface of the interface with the capping layer has been found to be a major cause of electromigration failure.
Conventional semiconductor manufacturing processes typically comprise forming a metal level having metal lines with varying widths. A metal level, therefore, typically comprises a collection of metal lines with line widths ranging from about 1× to about 50× of the smallest feature size. Such a smallest feature size can be a via having a diameter or cross sectional width of about 0.15 μm to about 10 μm. In implementing Cu metallization in narrow lines, e.g., lines having a width less than about 0.15 μm, it was found that voiding typically occurs after thermal annealing.
The primary weak surface responsible for electromigration failures is the interface between the Cu fill and capping layer. Rapid diffusion of Cu along this interface causes electromigration failures in both wide and narrow lines. Electromigration can be enhanced by reducing the speed of Cu diffusion along this interface by altering the nature of Cu, as by alloying, or by changing the capping layer. The introduction of certain alloying elements into Cu can reduce Cu diffusion albeit at an increase in resistance. This type of approach to reducing electromigration failure is best utilized in wide metal lines, because the increase in resistance will have a greater impact in narrow lines.
The use of a metal capping layer as an alternative to the conventional silicon nitride capping layer may improve the Cu-capping layer interface, thereby reducing rapid Cu diffusion at that junction. However, any advantage attendant upon employing a metal capping layer diminishes as the metal lines get wider, because Cu diffusion occurs not only along the Cu-capping layer interface but also along Cu grain boundaries. Grain boundary diffusion is not significant in narrow lines because there are very few grain boundaries in a narrow line. These various factors make it extremely difficult to fabricate highly reliable Cu interconnect systems with improved electromigration resistance.
Accordingly, there exists a need for methodology enabling implementation of Cu metallization with improved electromigration resistance in both relatively wide and relatively narrow lines, and reduced void generation in relatively narrow lines. There exists a particular need for such Cu metallization methodology in fabricating semiconductor devices having metal levels with varying line widths in the deep sub-micron regime.